Pitch multiplication spacers and methods of forming the same

ABSTRACT

Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

PRIORITY CLAIM

This application is a divisional of U.S. patent application Ser. No.12/827,506, filed Jun. 30, 2010, which is a divisional of U.S. patentapplication Ser. No. 11/219,346, filed Sep. 1, 2005 (now U.S. Pat. No.7,776,744), the entire disclosures of both of which are herebyincorporated by reference herein.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to the following: U.S. patent applicationSer. No. 10/934,778 to Abatchev et al., filed Sep. 2, 2004, entitledMethod for Integrated Circuit Fabrication Using Pitch Multiplication;and U.S. Patent Provisional Application No. 60/662,323 to Tran et al.,filed Mar. 15, 2005, entitled Pitch Reduced Patterns Relative ToPhotolithography Features.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to integrated circuit fabrication and,more particularly, to masking techniques.

2. Description of the Related Art

As a consequence of many factors, including demand for increasedportability, computing power, memory capacity and energy efficiency,integrated circuits are continuously being made more dense. The sizes ofthe constituent features that form the integrated circuits, e.g.,electrical devices and interconnect lines, are constantly beingdecreased to facilitate this scaling.

The trend of decreasing feature size is evident, for example, in memorycircuits or devices such as dynamic random access memories (DRAMs),flash memory, static random access memories (SRAMs), ferroelectric (FE)memories, etc. These memory devices typically comprise millions ofidentical circuit elements, known as memory cells. A capacitor-basedmemory cell, such as in conventional DRAM, typically consists of twoelectrical devices: a storage capacitor and an access field effecttransistor. Each memory cell is an addressable location that can storeone bit (binary digit) of data. A bit can be written to a cell throughthe transistor and can be read by sensing charge in the capacitor. Somememory technologies employ elements that can act as both a storagedevice and a switch (e.g., dendritic memory employing silver-dopedchalcogenide glass) and some nonvolatile memories do not requireswitches for each cell (e.g., magnetoresistive RAM). In general, bydecreasing the sizes of the electrical devices that constitute a memorycell and the sizes of the conducting lines that access the memory cells,the memory devices can be made smaller. Additionally, storage capacitiescan be increased by fitting more memory cells on a given area in thememory devices.

The continual reduction in feature sizes places ever greater demands onthe techniques used to form the features. For example, photolithographyis commonly used to pattern features, such as conductive lines. Theconcept of pitch can be used to describe the sizes of these featureswhen the pattern includes repeating features, as in arrays. Pitch isdefined as the distance between an identical point in two neighboringfeatures. These features are typically defined by spaces betweenadjacent features, which spaces are typically filled by a material, suchas an insulator. As a result, pitch can be viewed as the sum of thewidth of a feature and of the width of the space on one side of thefeature separating that feature from a neighboring feature. However, dueto factors such as optics and light or radiation wavelength,photolithography techniques each have a minimum pitch below which aparticular photolithographic technique cannot reliably form features.Thus, the minimum pitch of a photolithographic technique is an obstacleto continued feature size reduction.

“Pitch doubling” or “pitch multiplication” is one method for extendingthe capabilities of photolithographic techniques beyond their minimumpitch. A pitch multiplication method is illustrated in FIGS. 1A-1F anddescribed in U.S. Pat. No. 5,328,810, issued to Lowrey et al., theentire disclosure of which is incorporated herein by reference. Withreference to FIG. 1A, a pattern of lines 10 is photolithographicallyformed in a photoresist layer, which overlies a layer 20 of anexpendable material, which in turn overlies a substrate 30. As shown inFIG. 1B, the pattern is then transferred using an etch (preferably ananisotropic etch) to the layer 20, thereby forming placeholders, ormandrels, 40. The photoresist lines 10 can be stripped and the mandrels40 can be isotropically etched to increase the distance betweenneighboring mandrels 40, as shown in FIG. 1C. A layer 50 of spacermaterial is subsequently deposited over the mandrels 40, as shown inFIG. 1D. Spacers 60, i.e., the material extending or originally formedextending from sidewalls of another material, are then formed on thesides of the mandrels 40. The spacer formation is accomplished byperforming a spacer etch, i.e., by preferentially, directionally etchingthe spacer material from the horizontal surfaces 70 and 80, as shown inFIG. 1E. The remaining mandrels 40 are then removed, leaving behind onlythe spacers 60, which together act as a mask for patterning, as shown inFIG. 1F. Thus, where a given pitch previously included a patterndefining one feature and one space, the same width now includes twofeatures and two spaces, with the spaces defined by, e.g., the spacers60. As a result, the smallest feature size possible with aphotolithographic technique is effectively decreased.

While the pitch is actually halved in the example above, this reductionin pitch is conventionally referred to as pitch “doubling,” or, moregenerally, pitch “multiplication.” Thus, conventionally,“multiplication” of pitch by a certain factor actually involves reducingthe pitch by that factor. The conventional terminology is retainedherein.

It will be appreciated that etch processes may remove different parts ofa surface at different rates. For example, the trim etch of the mandrels40 may etch the sidewalls of the mandrels 40 at varying rates across asubstrate, due to local differences in temperatures that can cause localdifferences in etch rates. These non-uniformities can then betransferred to the spacers 60 formed on the sidewalls and, ultimately,lead to non-uniformities in features patterned in the substrate 30 usingthe spacers 60.

Moreover, the materials used to form the mandrels 40 should typically becompatible with various process steps, e.g., the materials are typicallymaterials for which a suitable selective isotropic etch is available (toperform the trim etch) and for which suitable selective anisotropicetches are available for various pattern formation and pattern transfersteps (e.g., for transferring patterns from overlying resist). In turn,the material for the mandrels 40 can limit the choice of later-depositedmaterials, e.g., spacer materials, since the deposition conditions forthe later-deposited materials should typically not adversely affect themandrels 40. The requirement of the isotropic etch, in addition to theother requirements for compatible etches and deposited materials, canlimit the choice of materials used in pitch multiplication, therebylimiting process latitude.

Accordingly, there is a need for methods for extending the capabilitiesof pitch multiplication.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a method is provided forsemiconductor processing. The method comprises providing a temporaryfeature over a substrate. The temporary feature comprises a firstmaterial. The first material is reacted with a chemical species to forma mask feature comprising the product of the reaction between the firstmaterial and the chemical species. Unreacted first material issubsequently selectively removed.

According to another aspect of the invention, a method is provided forforming a memory device. The method comprises defining a pattern in aselectively definable layer over a substrate. The pattern is transferredfrom the selectively definable layer to an underlying layer of temporarymaterial to form a plurality of temporary placeholders in the layer oftemporary material across a region over the substrate. Some of thetemporary material is converted into an other material to form aplurality of spacers. The mask material forms a plurality of maskfeatures and temporary material that is unconverted is selectivelyremoved. The substrate is processed through a mask pattern defined bythe plurality of spacers.

According to another aspect of the invention, a method is provided forforming an array of repeating features in an integrated circuit. Themethod comprises lithographically defining a plurality of resistfeatures in a resist layer over a substrate to form a pattern. Theresist features each have a width defined by lithographically. Thepattern is transferred to a layer of mandrel material under the resistlayer to form a plurality of mandrels on a level over the substrate. Themandrels each have a width substantially equal to a width of the resistfeatures. A plurality of spacers is formed on the level of the mandrelswithout etching the mandrels after transferring the pattern. Thedistance between the spacers is less than the width of the mandrels. Thepattern defined by the spacers is transferred to the substrate to formthe array of repeating features.

According to yet another aspect of the invention, a method is providedmethod for fabricating an integrated circuit. The method comprisesproviding a mandrel in a region of the integrated circuit. A layer ofmaterial is deposited over the mandrel. The layer of material isisotropically etched to leave exposed spacers at the sides of themandrel.

According to another aspect of the invention, an intermediate maskpattern overlying a partially fabricated integrated circuit is provided.The mask pattern comprises a plurality of spaced mandrels, which eachhave a cap layer overlying its top surface. A layer of pre-spacermaterial overlies each cap layer. The partially fabricated integratedcircuit further comprises spacers on sides of each of the mandrel. Thespacers comprise a combination of the pre-spacer material and themandrel material. The pre-spacer material also extends betweenneighboring spacers.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from the Detailed Description ofthe Preferred Embodiments and from the appended drawings, which aremeant to illustrate and not to limit the invention, and wherein:

FIGS. 1A-1F are schematic, cross-sectional side views of a sequence ofmasking patterns for forming conductive lines, in accordance with aprior art pitch doubling method;

FIG. 2 is a schematic cross-sectional side view of a partially formedintegrated circuit, in accordance with preferred embodiments of theinvention;

FIG. 3 is a schematic cross-sectional side view of the partially formedintegrated circuit of FIG. 2 after forming features in a photoresistlayer, in accordance with preferred embodiments of the invention;

FIG. 4 is a schematic, cross-sectional side view of the partially formedintegrated circuit of FIG. 3 after etching through a hard mask layer, inaccordance with preferred embodiments of the invention;

FIG. 5 is a schematic, cross-sectional side view of the partially formedintegrated circuit of FIG. 4 after transferring a pattern from the hardmask layer to a layer of mandrel material to form a pattern of mandrelsin the temporary layer, in accordance with preferred embodiments of theinvention;

FIG. 6 is a schematic, cross-sectional side view of the partially formedintegrated circuit of FIG. 5, after depositing a layer of a pre-spacermaterial, in accordance with preferred embodiments of the invention;

FIG. 7 is a schematic, cross-sectional side view of the partially formedintegrated circuit of FIG. 6 after reacting the layer of the pre-spacermaterial to form spacers on the mandrel sidewalls, in accordance withpreferred embodiments of the invention;

FIG. 8 is a schematic, cross-sectional side view of the partially formedintegrated circuit of FIG. 7 after selectively removing unreactedpre-spacer material, in accordance with preferred embodiments of theinvention;

FIG. 9 is a schematic, cross-sectional side view of the partially formedintegrated circuit of FIG. 8 after removing a hard mask layer, inaccordance with preferred embodiments of the invention;

FIG. 10 is a schematic, cross-sectional side view of the partiallyformed integrated circuit of FIG. 9 after selectively removing unreactedmandrel material, in accordance with preferred embodiments of theinvention;

FIG. 11 is a schematic, cross-sectional side view of the partiallyformed integrated circuit of FIG. 10 after transferring a pattern formedby the spacers to a hard mask layer underlying the spacers, inaccordance with preferred embodiments of the invention;

FIG. 12 is a schematic, cross-sectional side view of the partiallyformed integrated circuit of FIG. 11 after removing the spacers, inaccordance with preferred embodiments of the invention;

FIG. 13 is a schematic, cross-sectional side view of the partiallyformed integrated circuit of FIG. 12 after transferring the pattern inthe masking layer to an underyling substrate, in accordance withpreferred embodiments of the invention

FIG. 14 is a schematic, cross-sectional side view of a partially formedintegrated circuit having hard a mask and additional masking layersdisposed between the spacers and the substrate, in accordance withpreferred embodiments of the invention;

FIG. 15 is a schematic, cross-sectional side view of the partiallyformed integrated circuit of FIG. 14 after transferring the spacerpattern into the additional masking layers and an underyling substrate,in accordance with preferred embodiments of the invention; and

FIG. 16 is a schematic, cross-sectional side view of the partiallyformed integrated circuit of FIG. 5 after forming spacers on sides ofthe mandrels by a gas phase reaction, in accordance with some preferredembodiments of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In preferred embodiments of the invention, in a masking process, maskfeatures, such as spacers, are formed by a reaction with a temporaryfeature, such as a mandrel. Preferably, the spacers are formed at thesides of mandrels and a trim etch of the mandrels is not needed. Themandrels are preferably reacted with at least one other material orchemical species to form the spacers, which comprise spacer materialthat is a product of the reaction. A cap layer is preferably formed overthe top, horizontal surface of the mandrels to inhibit reactions on thatsurface. Thus, the reactions preferably occur at the sides of themandrels and convert the sidewall mandrel material into spacer material.Unreacted mandrel material is then preferably removed, to leave apattern of free-standing spacers. Preferably, the spacers are formedwithout a spacer etch, i.e., without performing a directional etch thatpreferentially removes spacer material from horizontal surfaces. Afterremoving the mandrel material, the pattern of free-standing spacers canbe used in a mask for subsequently processing an underlying substrate.

The conversion of mandrel material into spacer material can beaccomplished by various processes, including, e.g., oxidation,nitridation, silicidation and polymerization. For example, a layer of amaterial is formed on the sides the mandrels (e.g., by performing aconformal blanket deposition over the mandrels) and the mandrels aremade to react with that layer of material by, e.g., performing ananneal. In other embodiments, the mandrels can be exposed to one or moregaseous reactants to form the spacer material, or the mandrels can beexposed to energy (e.g., light) or other agents (e.g., catalysts) toconvert the exposed mandrel material into another material by, e.g.,polymerizing or cross-linking the exposed sidewalls of the mandrelmaterial.

Advantageously, because the spacers are formed by converting part of themandrels into spacer material, a trim of the mandrels is not necessary.The spacers are formed extending into the mandrels and, thus, can bemade closer together than would be the case if the spacers were formedon the sidewalls of the mandrels. The extent of the spacer formationreaction can influence both the thickness of the spacers and the spacingtherebetween. Advantageously, the spacer separation can be similar tothe separation achieved after performing a mandrel trim etch in atypical pitch multiplication process. Moreover, because a trim etch isnot necessary, the selection of materials for the mandrel is not limitedto materials compatible with the trim etch. In addition, a spacer etchcan advantageously be avoided. It will be appreciated that a spacer etchcan round the top edges of a spacer. Such rounding can be undesirable asit, e.g., effectively reduces the aspect ratio of the spacers and/orencourages an uneven distribution of etchants or other materials duringapplication of etchants or other material to any layers underlying thespacers. Advantageously, spacers formed according the preferredembodiments can have a more uniform, square shape. Moreover, a spaceretch can be more aggressive and can erode underlying material to agreater extent than the removal of unreacted material in the preferredembodiments.

Reference will now be made to the Figures, wherein like numerals referto like parts throughout. It will be appreciated that the Figures arenot necessarily drawn to scale.

Initially, a sequence of layers of materials is formed to allowformation of spacers over a substrate.

FIG. 2 shows a cross-sectional side view of a partially formedintegrated circuit 100. While the preferred embodiments can be used toform any integrated circuit, they are particularly advantageouslyapplied to forming devices having repeating patterns or arrays ofelectrical devices, including memory cell arrays for volatile andnon-volatile memory devices such as DRAM, phase change RAM, programmableconductor (PCRAM), ROM or flash memory, including NAND flash memory, orintegrated circuits having logic or gate arrays. For example, the logicarray can be a field programmable gate array (FPGA) having a core arraysimilar to a memory array and a periphery with supporting logics.Consequently, the integrated circuit 100 can be, e.g., a memory chip ora processor, which can include both a logic array and embedded memory,or any other integrated circuit having a logic or a gate array.

With continued reference to FIG. 2, various masking layers 120-150 arepreferably provided above a substrate 110. It will be appreciated thatthe substrate 160 can be a silicon wafer or any structure or layer ofmaterial overlying a wafer. For example, the substrate 100 can comprisean insulating film.

The layers 120-150 will be etched to form a mask for patterning thesubstrate 110, as discussed below. Materials for the layers 120-150 arepreferably chosen based upon consideration of the chemistry and processconditions for the various pattern forming and pattern transferringsteps discussed herein. Because the layers between a topmost selectivelydefinable layer 120 and the substrate 110 preferably function totransfer a pattern derived from the selectively definable layer 120 tothe substrate 110, the layers 130-150 between the selectively definablelayer 120 and the substrate 110 are preferably chosen so that they canbe selectively etched relative to other exposed materials at variousstages, as described below. It will be appreciated that a material isconsidered selectively, or preferentially, etched when the etch rate forthat material is at least about 5 times greater, preferably at leastabout 10 times greater, more preferably at least about 20 times greaterand, most preferably, at least about 40 times greater than that forsurrounding materials. Because a goal of the layers 120-150 overlyingthe substrate 110 is to allow well-defined patterns to be formed in thatsubstrate 110, it will be appreciated that one or more of the layers120-150 can be omitted or substituted if suitable other materials,chemistries and/or process conditions are used. For example, anantireflective coating can be formed between the layers 120 and 130 insome embodiments where the resolution enhancement properties of such alayer are desired. In other embodiments, discussed further below,additional masking layers can be added between the layer 150 and thesubstrate 110 to form a mask having improved etch selectivity relativeto the substrate 110. Optionally, if appropriate etch chemistries areavailable, the layer 150 can be omitted and the spacers 175 (FIG. 10)can be used as a mask to, e.g., pattern the substrate without anyintervening materials. Exemplary materials for the various layersdiscussed herein include silicon oxide, silicon nitride, silicon,amorphous carbon, dielectric antireflective coatings (DARC, silicon richsilicon oxynitride), and organic bottom antireflective coatings (BARC),each of which can be selectively etched relative to at least 2 or 3 ofthe other materials, depending upon the application.

In addition to selecting appropriate materials for the various layers,the thicknesses of the layers 120-150 are preferably chosen dependingupon compatibility with the etch chemistries and process conditionsdescribed herein. For example, when transferring a pattern from anoverlying layer to an underlying layer by selectively etching theunderlying layer, materials from both layers are removed to some degree.Preferably, the upper layer is thick enough so that it is not worn awayover the course of the pattern transfer.

The selectively definable layer 120 preferably overlies a hard masklayer 130, which preferably can function as a cap layer to shieldmandrels 145 (FIG. 5) from reactive agents, as discussed below. Thelayer 130 overlies a mandrel layer 140, which overlies a second hardmask, or etch stop, layer 150, which overlies the substrate 110 to beprocessed (e.g., etched) through a mask. The selectively definable layer120 is preferably photodefinable, e.g., formed of a photoresist,including any photoresist known in the art. For example, the photoresistcan be any photoresist compatible with 157 nm, 193 nm, 248 nm or 365 nmwavelength systems, 193 nm wavelength immersion systems, extremeultraviolet systems (including 13.7 nm wavelength systems) or electronbeam lithographic systems. In addition, maskless lithography, ormaskless photolithography, can be used to define the selectivelydefinable layer 120. Examples of preferred photoresist materials includeargon fluoride (ArF) sensitive photoresist, i.e., photoresist suitablefor use with an ArF light source, and krypton fluoride (KrF) sensitivephotoresist, i.e., photoresist suitable for use with a KrF light source.ArF photoresists are preferably used with photolithography systemsutilizing relatively short wavelength light, e.g., 193 nm. KrFphotoresists are preferably used with longer wavelength photolithographysystems, such as 248 nm systems. In other embodiments, the layer 120 andany subsequent resist layers can be formed of a resist that can bepatterned by nano-imprint lithography, e.g., by using a mold ormechanical force to pattern the resist.

The material for the hard mask layer 130 preferably comprises aninorganic material. Exemplary materials include, without limitation,silicon oxide and silicon nitride. In the illustrated embodiment, thehard mask layer 130 comprises silicon nitride. The mandrel layer 140 ispreferably formed of a material that can be converted into a spacermaterial, which in turn offers good etch selectivity relative to theunreacted mandrel material, the hard mask layer 130 and materialunderlying the spacer material. In the illustrated embodiment, themandrel material is silicon.

The material for the second hard mask layer 150 is preferably chosenbased upon the material used for the spacers 175 (FIG. 11) and for theunderlying substrate 110. Where the layer 150 is used as a mask to etchthe substrate 110, the layer 150 is preferably formed of a material thatis resistant to the desired processing (e.g., etching, doping,oxidizing, etc.) of the substrate 110 to be conducted through the maskand can be selectively etched relative to the spacers 175 (FIG. 11). Forexample, the second hard mask layer 150 can be a nitride, e.g., siliconnitride, or can be an oxide, e.g., silicon oxide. In the illustratedembodiment, the second hard mask layer 150 comprises silicon oxide.

The various layers discussed herein can be formed by various methodsknown in the art. For example, spin-on-coating processes can be used toform photodefinable layers, BARC, and spin-on dielectric oxide layers.Various vapor deposition processes, such as sputtering, chemical vapordeposition (CVD) and/or atomic layer deposition (ALD), can be used toform various hard mask, cap and mandrel layers. In addition, somelayers, e.g., the layer 140, can be reacted to form other layers. Forexample, rather than depositing a silicon nitride layer using siliconand nitrogen precursors, the top surface of the silicon layer 140 can benitrided using a nitrogen precursor to form a silicon nitride layer,which can serve as a hard mask layer, or a cap layer for thesubsequently produced mandrel (as will be better understood in view ofthe discussion below).

Having formed a desired stack of layers, a pattern of spacers is nextformed.

With reference to FIG. 3, a pattern comprising spaces or trenches 122,which are delimited by features 124 formed of photodefinable material,is formed in the photodefinable layer 120. The trenches 122 can beformed by, e.g., photolithography with 248 nm or 193 nm light, in whichthe layer 120 is exposed to radiation through a reticle and thendeveloped. The remaining photodefined material forms mask features suchas the illustrated lines 124 (shown in cross-section only) after beingdeveloped. Advantageously, the lines 124 can be formed having widths ofabout 120 nm or less, or about 80 nm or less, to form spacers having apitch of about 100 nm or less.

With reference to FIG. 4, the pattern of photoresist features 124 andtrenches 122 is transferred to the hard mask layer 130. This transfer ispreferably accomplished using an anisotropic etch, such as an etch usinga CF₄, CF₄/H₂, CF₄/O₂, SF₆ or NF₃-containing plasma, although a wet(isotropic) etch may also be suitable if the hard mask layer 130 issufficiently thin to be etched through without undesirably wideningspaces in the transferred pattern.

With reference to FIG. 5, the pattern in the photodefinable layer 120and the hard mask layer 130 is transferred to the mandrel layer 140 toform mandrels, or temporary placeholders, 145. The transfer ispreferably accomplished using an anisotropic etch employing, e.g.,HBr/HCl or CHCl₃/Cl₂-containing plasma. The widths of the mandrels 145are preferably substantially similar to the widths of the lines 124,e.g., the mandrels 145 preferably have a width of about 120 nm of less,or about 80 nm or less.

With reference to FIG. 6, pre-spacer material, i.e., material to bereacted to form spacers, is deposited on the sidewalls of the mandrels145. Preferably, the pre-spacer material is blanket deposited as a layer170 on the mandrels 145. In the illustrated embodiment, the pre-spacermaterial that forms the layer 170 is titanium. The deposition can beaccomplished by various methods known in the art, including, e.g., CVDand ALD. The thickness of the layer 170 is preferably chosen to providesufficient material to form spacers 175 (FIG. 7) of the desired widthafter reaction of the pre-spacer material 170 with the mandrels 145, asdiscussed below.

With reference to FIG. 7, the titanium pre-spacer layer 170 and themandrels 145 are next reacted with one another to form spacers 175,composed of a titanium silicide in the illustrated embodiment. It willbe appreciated that the mandrels 145 are preferably provided with a caplayer to focus the reaction on the sidewalls of the mandrels 145. In theillustrated embodiment, the hard mask layer 130 preferably acts as thecap layer to prevent the top of the mandrels 145 from being reacted, bypreventing contact between the titanium pre-spacer layer 170 and the topsurface of the mandrels 145. In other embodiments, the cap layer can beseparately formed, e.g., by deposition on or reaction of the top of themandrels 145, whether or not the hard mask layer 130 is present.

Preferably, the layer 170 and the mandrels 145 are subjected to anelevated temperature, e.g., an anneal, to cause a self-alignedsilicidation reaction. For example, the partially fabricated integratedcircuit 100 can be subjected to rapid thermal processing (RTP) at atemperature of about 550-800° C., more preferably, about 650-680° C.,for about 5-90 seconds, more preferably, about 20-60 seconds.

It will be appreciated that the extent of the reaction and the amount oftitanium in the layer 170 that reacts with the silicon of the mandrels145 is related to the temperature and duration of the anneal. Thus,advantageously, reaction conditions, such as the temperature andduration of the anneal, can be selected depending upon the width and/orseparation distance desired for the spacers 175. For example, themandrels 145 and the layer 170 can be reacted until the separation isabout 80 nm or less or, more preferably, about 50 nm or less.

In other embodiments, the parts of the titanium layer 170 at thesidewalls of the mandrels 145 are preferably fully reacted.Advantageously, fully reacting these parts allows for a larger processwindow for the anneal and good control over the widths of the spacers175, since the thickness of the layer 170 typically places a limit onthe maximum width of the spacers 175 formed by the reaction. Forexample, by depositing the layer 170 to a given width, the durationand/or temperature of the anneal can be allowed to exceed the durationand/or temperature needed to form spacers 175 of that width, since theamount of material (e.g., the width) of the layer 170 typically limitsthe growth of the spacers 175, particularly in the direction of thelayer 170.

With reference to FIG. 8, unreacted titanium in the layer 170 isselectively removed to leave the spacers 175 at the sides of themandrels 145. The removal can be accomplished by wet or dry etches. Awet etch can have advantages for reduced costs and less damage to thestructure of the spacers 175. An example of a suitable etch is a wetetch comprising H₂O, H₂O₂ and NH₄OH. Preferably, the spacers 175 aresublithographic, i.e., they have a critical dimension, e.g., width, thatis below the resolution limit of the photolithographic technique usedfor forming the spacer pattern, in this case, the photolithographictechnique used to pattern the layer 120.

With reference to FIG. 9, the silicon nitride cap layer 130 isselectively removed relative to the spacers 175. This removal can beaccomplished using a dry etch or a wet etch, e.g., using hot phosphoricacid.

Next, as shown in FIG. 10, unreacted mandrel material is selectivelyremoved to form a pattern of free-standing spacers 175. Dry or wetetches can be employed for this removal. An exemplary wet etch comprisesHF, HNO₃ and H₂O. A hard mask layer 150 can be provided underlying thespacers 175, to protect the substrate 110 and to allow unreacted mandrelmaterial to be removed without unintentionally removing material in thesubstrate 110. Thus, advantageously, the spacers 175 can be formedhaving a pitch that is roughly half that of the photoresist lines 124and spaces 122 (FIG. 3) originally formed by photolithography. Where thephotoresist lines 124 had a pitch of about 200 nm, spacers 175 having apitch of about 100 nm or less can be formed.

It will be appreciated that because the spacers 175 are formed in thesidewalls of the mandrels 145, the spacers 175 generally follow theoutline of the mandrels 145 and, so, typically form a closed loop. Itwill be appreciated that where the pitch multiplied pattern is used toform features such as conductive lines, additional processing steps canbe used to cut off or otherwise prevent transfer of the pattern at theends of these loops, so that each loop forms two individual,non-connected lines. This can be accomplished, for example, bydepositing a layer of a protective material over the loops, patterningthe protective layer to form a protective mask around the parts of thelines to be maintained, and then etching away the unprotected parts,e.g., the ends, of the loops. A suitable method for cutting off the endsof the loops is disclosed in U.S. patent application Ser. No. 10/931,771to Tran et al., filed Aug. 31, 2004, the entire disclosure of which isincorporated be reference herein.

With reference to FIG. 11, in addition to protecting the substrate 110during a spacer removal, the hard mask layer 150 preferably allows forimproved etch selectivity relative to the substrate 110, in cases wherethe pattern of spacers 175 is to be transferred to the substrate 110. Asdiscussed above, the hard mask layer 150 is formed of silicon oxide inthe illustrated embodiment. The pattern of spacers 175 is preferablytransferred to the layer 150 using an anisotropic etch, e.g., an etchcontaining CHF₃, CF₄ or C₂F₆ plasma. If the hard mask layer 150 issufficiently thin, it will be appreciated that a wet etch may also beused to accomplish the pattern transfer with minimal undercutting.

Next, the hard mask layer 150 can be used to pattern the underlyingsubstrate 110.

It will be appreciated that the spacers 175 can be removed before orafter etching the substrate 110. Preferably, where the material of thehard mask layer 150 offers good etch selectivity relative to thematerial of the substrate 110, e.g., where the spacers 175 are notneeded to supplemental the hard mask layer 150, the spacers 175 can beremoved before the pattern is transferred to the substrate 110. Thespacer removal can be accomplished using, e.g., a dilute HF wet etch.Advantageously, the spacer removal reduces the aspect ratio of thespaces through which processing is conducted, e.g., through whichetchants must travel to reach the substrate 110 and minimizes thepossibility of alterations in the pattern caused by collapse ordeformation of the spacers 175, especially where the spacers 175 arevery tall and/or narrow. Thus, as shown in FIG. 11, the spacers 175 canbe removed to facilitate the etch of the substrate.

With reference to FIG. 13, the pattern in the hard mask layer 150 can betransferred to the substrate 110 using, e.g., an etch or combination ofetches selective for the material(s) of the substrate 110. In additionto etching the substrate through masks, in other embodiments, othertypes of processing through the mask in the layer 150 are also possible.Non-limiting examples of other processes include implantation, diffusiondoping, lift-off patterned deposition, oxidation, nitridation, etc.

With reference to FIG. 14, in other embodiments, especially where thesubstrate 110 is difficult to etch or where prolonged processing throughthe mask is desired, one or more additional intervening layers ofmasking material can be formed between the spacers 175 and the substrate110. For example, an additional layer 160 can be provided, as discussedin co-pending U.S. Patent Provisional Application No. 60/662,323 to Tranet al., filed Mar. 15, 2005, entitled Pitch Reduced Patterns Relative ToPhotolithography Features, disclosure of which is incorporated herein byreference.

With continued reference to FIG. 14, the layer 150 preferably comprisesa material that has good etch selectively relative to the spacers 175,the layer 160 and the mandrels 145 (FIG. 9). The layer 160 is preferablyformed of amorphous carbon, which is advantageously resistant to manyetch chemistries for removing silicon materials in the substrate 110.

With reference to FIG. 15, the pattern defined by the spacers 175 can betransferred to the layer 160, which then serves as the primary mask 160for patterning the substrate 110. Advantageously, in other embodiments,due to the availability of extreme selectivity when etching amorphouscarbon, a patterned hard mask layer 150 can be used to transfer thepattern from the layer 150 to the layer 160 after removal of the spacers175, so that the mask used to transfer the pattern to the primarymasking layer 160 has lower and more uniform aspect ratio features. Inother embodiments, in conjunction with suitable other materials, thehard mask layer 150 can itself be formed of amorphous carbon.

In yet other embodiments, there may be no intervening layers, e.g., nohard mask layer 150, between the substrate 110 and the spacers 175. Insuch cases, especially where the spacer material has good etchselectivity relative to the substrate, the substrate 110 can beprocessed through the pattern of spacers 175 without any interveninghard mask layers.

It will be appreciated that the formation of spacers according to thepreferred embodiments offers numerous advantages. For example, a mandreltrim etch is not necessary and the spacer non-uniformities that can becaused by such a trim etch can be eliminated. Instead, deposition of thepre-spacer layer 170 and the extent of a spacer formation reaction,e.g., an anneal, determine both the spacer width and the spacer spacing.Moreover, because a trim etch is not performed, the range of materialsthat can be used to form mandrels may be expanded, as requirements forcompatibility with trim etches is removed. Thus, processing flexibilitycan be increased. In addition, a directional spacer etch is notnecessary, allowing advantages with respect to forming spacers 175 withsymmetrically shaped shoulders and to minimizing damage to underlyinglayers.

While a spacer etch is advantageously not necessary in the preferredembodiments, in some arrangements, a spacer etch can be performed on thelayer 170 of pre-spacer material to form spacer features, formed ofpre-spacer material, on the sides of the mandrels before reacting thepre-spacer material and the mandrel material. These spacer features canthen be reacted with the mandrel material to form the spacers 175, whichare selectively etchable relative to the mandrel material and underlyingmaterials.

It will also be appreciated that, while discussed with reference toparticular processing steps and materials in the illustrated embodiment,various modifications are possible. For example, various silicides inaddition to titanium silicide can be used to form the spacers. Examplesof other metals to form metal silicides include tantalum, hafnium, andnickel. In the example above, these metals can be deposited over themandrels and annealed to form a metal silicide. In other arrangements,the combination of materials can be reversed. For example, the mandrels145 can be metallic and a silicon layer is deposited over the mandrelsto form a metal silicide. In addition, the mandrels 145 can compriseamorphous carbon and the layer 170 can comprise various other materialsreactive with amorphous carbon. For example, the layer 170 can comprisesilicon to form silicon carbide spacers 175, or the layer 170 cancomprise a metal to form a metal carbide.

With reference to FIG. 16, it will be appreciated that while theformation of the spacers 175 is illustrated as a solid state reaction inwhich a deposited metal layer reacts with the mandrels, the spacers 175can be formed by various processes other than reactions between solidstate reactants. In some embodiments, the mandrels 145 can be reactedwith a gaseous reactant to form spacers, including spacers that are notsilicides. For example, a silicidation of a silicon mandrel 145 can beaccomplished by exposing the mandrels 145 to a gaseous metal reactant(e.g., TiCl₄, WF₆, etc.), or a gas phase silicidation of a metal mandrel145 can be accomplished by exposing the mandrels 145 to a gaseoussilicon reactant (e.g., SiH₄). In addition, silicon oxide spacers can beformed by exposing silicon mandrels to an oxidant or, where the caplayer is a suitable material other than silicon nitride, silicon nitridecan be formed by exposing silicon mandrels to a reactive nitrogenspecies. In other embodiments, the mandrels 145 can be a carbon species,such as amorphous carbon, resist, or carbon-doped materials (e.g., asdisclosed in U.S. Pat. No. 6,515,355, the entire disclosure of which isincorporated by reference herein) which is converted to a polymer orcross-linked to form spacers 175. The conversion can be caused byexposure to energy (e.g., light) or other agents (e.g., catalysts).After the spacers 175 are formed, the partially fabricated integratedcircuit 100 can be processed as discussed above regarding FIGS. 9-15.

Additionally, while two materials are discussed above for ease ofillustration and description, it will be appreciated that more than twomaterials can be reacted to form a desired spacer material, e.g.,SiO_(x)N_(y) formed by a reaction with gas phase reactants. Theseadditional materials can be reacted by, e.g., forming depositingmultiple layers of pre-spacer materials over one another and thenperforming an anneal and/or by depositing a single layer of pre-spacermaterial, performing an anneal to react that layer with the mandrelmaterial and then depositing one or more additional layers of pre-spacermaterial and then performing an anneal. In other embodiments, theadditional materials can be introduced as gaseous reactants as analternative to or in additional to depositing layers of pre-spacermaterial.

Moreover, while trim etches are preferably not performed in theformation of the mandrels, a trim etch can be performed if desired. Forexample, the photoresist layer can be subjected to a trim etch afterbeing developed, and/or the mandrels can be subjected to a trim etch.Such a trim etch may be useful to form spacers that are exceptionallyclose to together.

Additionally, the cap layer can be formed after forming the mandrels.For example, the tops of the mandrels may be reacted with directionallyapplied reactants, e.g., in a process similar to ion implantation, toform the cap layer.

Moreover, the spacers are formed without a cap layer for the mandrels.For example, a metal layer can be conformally deposited over themandrels and both the top and sides of the mandrels can be reacted. Thereacted top parts can them be removed, e.g., by a directional dry etchor by filling the empty spaces between the mandrels with a fillermaterial, performing chemical mechanical polishing to remove the topparts and then removing the filler material.

As with the spacers, it will also be appreciated that other materialscan be used for the various other layers and parts discussed herein.Preferably, any other materials that may be used offer the appropriateetch selectivity relative to the materials that are exposed during theselective etch steps, as discussed above. Moreover, the substrate 110can comprise different materials, e.g., layers of different materials,or different materials in different lateral regions of the substrate. Totransfer the pattern defined by the spacers to such a substrate, asuccession of different chemistries, preferably dry-etch chemistries,can be used to successively etch through these different materials, if asingle chemistry is not sufficient to etch all the different materials.

It will also be appreciated that, depending upon the chemistry orchemistries used, overlying spacers and hard mask layers may be etched.In some cases, the additional masking layer 160 (FIG. 14) is preferablyused for superior etch selectivity. Using amorphous carbon for theprimary mask layer 160 advantageously offers excellent resistance toconventional etch chemistries, especially those used for etchingsilicon-containing materials. Thus, the primary mask layer 160 caneffectively be used as a mask for etching through a plurality ofsubstrate layers, or for forming high aspect ratio trenches.

Also, the masks discussed herein can be used to form various integratedcircuit features, including, without limitation, conductive interconnectlines, landing pads and parts of various electrical devices, such ascapacitors and transistors, particularly for memory and logic arrays, orflat panel displays, in which dense repeating patterns are desirable. Assuch, while illustrated as lines with regular spacing and regular widthsfor ease of illustration, the masks can have features with variablespacing. Also, while illustrated with spacers formed on a single level,in other embodiments, spacers can be formed on multiple vertical levelsand consolidated on a single level to form a mask pattern.

In addition, the pitch of the pattern formed in the photoresist layer120 can be more than doubled. For example, the pattern can be furtherpitch multiplied by using the spacers 175 as mandrels for a conventionalpitch multiplication process in which additional spacers are formedaround the spacers 175, then the spacers 175 are removed, then spacersare formed around the spacers that were formerly around the spacers 175,and so on.

The preferred embodiments can also be employed multiple times throughoutan integrated circuit fabrication process to form features in aplurality vertical levels, which may be vertically contiguous ornon-contiguous and vertically separated. In such cases, each of theindividual levels to be patterned would constitute a substrate 110. Inaddition, some of the preferred embodiments can be combined with otherof the preferred embodiments, or with other masking methods known in theart, to form features on different areas of the same substrate 110 or ondifferent vertical levels.

Accordingly, it will be appreciated by those skilled in the art thatthese and various other omissions, additions and modifications may bemade to the methods and structures described above without departingfrom the scope of the invention. All such modifications and changes areintended to fall within the scope of the invention, as defined by theappended claims.

1-14. (canceled)
 15. An intermediate mask pattern overlying a partiallyfabricated integrated circuit, comprising: a plurality of spacedmandrels formed of a mandrel material; a cap layer overlying a topsurface of each of the mandrels; a layer of pre-spacer materialoverlying each cap layer; and spacers on sides of each of the mandrels,wherein the spacers comprise a combination of the pre-spacer materialand the mandrel material, wherein the pre-spacer material extendsbetween neighboring spacers.
 16. The intermediate mask pattern of claim15, wherein the cap layer comprises silicon oxide or silicon nitride.17. The intermediate mask pattern of claim 15, wherein the mandrelcomprises silicon.
 18. The intermediate mask pattern of claim 15,wherein the spacers comprise a metal silicide.
 19. The intermediate maskpattern of claim 18, wherein the metal of the metal silicide is selectedfrom the group consisting of tantalum, hafnium, and nickel.
 20. Theintermediate mask pattern of claim 15, wherein the spacers aresublithographic features.
 21. The intermediate mask pattern of claim 15,wherein the spacers have a separation of 80 nm or less.
 22. Theintermediate mask pattern of claim 21, wherein the separation is 50 nmor less.
 23. The intermediate mask pattern of claim 18, wherein thespacers comprise a metal silicide.
 24. The intermediate mask pattern ofclaim 15, wherein the layer of spacer material extends continuously overthe plurality of spaced mandrels.
 25. The intermediate mask pattern ofclaim 15, further comprising: a hard mask layer underlying the spacers;and a substrate underlying the hard mask layer.
 26. The intermediatemask pattern of claim 25, wherein the substrate is a silicon wafer. 27.The intermediate mask pattern of claim 25, wherein the hard mask layercomprises silicon.
 28. The intermediate mask pattern of claim 27,wherein the hard mask layer comprises silicon oxide.
 29. Theintermediate mask pattern of claim 28, further comprising an amorphouslayer between the hard mask layer and the substrate.
 30. Theintermediate mask pattern of claim 15, wherein the mandrels have a widthof 120 nm of less.
 31. The intermediate mask pattern of claim 30,wherein the mandrels have a width of 80 nm or less.
 32. The intermediatemask pattern of claim 15, wherein the partially fabricated integratedcircuit is a partially formed memory.
 33. The intermediate mask patternof claim 15, wherein the memory is flash memory.
 34. The intermediatemask pattern of claim 15, wherein the partially fabricated integratedcircuit is a partially formed processor.